1. Field of The Invention
This invention relates to planarization of topographical features of integrated circuits and in particular to the use of ion bombardment to obtain multilevel interconnect dielectric planarization.
2. Background of the Invention
In the future, planarization will relax lithographic registration requirements and improve interconnect density. More importantly, it will relax the depth of field requirements since it is easier to maintain the sharpness of the topographical features when the surface is even. Furthermore, planarization relaxes overetch requirements in anisotropic metal etching. However, planarization which would introduce these advantages can not be achieved using, for example, resist etchback/SOG techniques. U.S. Pat. No. 4,670,091, issued to Thomas et al. on June 2, 1987, teaches a process performing vias for multilevel interconnects in integrated circuits wherein a conformal dielectric layer is formed by CVD or sputtering to cover interconnects and vias. The dielectric layer is then etched back to form a substantially planar surface. However methods such as these do not provide perfect planarization.
For example, the present methods of planarizing integrated circuit topologies do not planarize tightly pitched features well. Additionally, present processes do not planarize large and isolated features of integrated circuit topology very well. Finally, the present processes do not bring dielectric features to the same level over the entire surface of the wafer being planarized.
One reason for this is that the sacrificial fluids used in planarization are affected by the topographical density. In prior art methods, the sacrificial fluid is spun onto the silicon dioxide surface to be planarized. This method is effective for obtaining local planarization, but it is more satisfactory for planarizing some types of topographical features than others. Locally, effective planarization for leveling features on the order of five to ten microns is possible.
For example, this method does not effectively level large isolated finely pitched features. In tightly spaced features, the sacrificial fluid is held in the tight features by surface tension. Thus densely packed tightly pitched features get only an intermediate quality of planarization with respect to isolated features. Isolated features are planarized more poorly the tightly spared features. For example, a very thin layer of fluid accumulates over a fine line by itself in an open field. During the planarization the line may be exposed by etching. Thus it is very beneficial to generate a dielectric layer over all features wherein the dielectric layer is of uniform height at all points. However, there are still some problems with using this method to planarize large pads on the order of 120 microns in size. This problem arises because the wafer is spun after the sacrificial fluid is supplied to the surface of the wafer causing a varying and somewhat thicker level of the fluid in the center of a large pad compared to the thickness seen in a densely spaced region of fine features on the order of microns in size.
It is known in the art (IBM BSQ) to perform a topographical wafer planarization process wherein ions are directed to the surface of the topographical wafer at an angle of 90 degrees with respect to the wafer plane. This method achieves some degree of planarization. However, the edges of many of the topographical features of the wafers were knocked off by this process, exposing the underlying metal.